RE: [sv-bc] logical operation on vectors

Personally, I recommend never to use the logical AND/OR operators. They
are redundant. Everything you can do with them you can do also with the
corresponding bit-wise operators (at least in Verilog. Is there a
difference in SV?)

I would have been happier if the logical AND/OR operators did not exist
in Verilog.

Shalom

> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On
> Behalf Of Steven Sharp
> Sent: Wednesday, January 25, 2006 9:16 PM
> To: sv-bc@eda.org; Nasim.Hussain@sun.com
> Subject: Re: [sv-bc] logical operation on vectors
> 
> 
> >From: Nasim Hussain <Nasim.Hussain@sun.com>
> 
> >	always_comb begin
> >	   a = x || y;
> >	   b = x && y;
> >	end
> >
> >
> >will simulator's parser issue a warning or an error as i am
> doing a
> >logical (and not bit-wise) OR / AND operation on 2 vectors ?
> 
> No, applying the logical operators to vectors is perfectly
> legal and
> well-defined.
> 
> 
> >	always_comb begin
> >	   a = !(x == 2'b00) || !(y == 2'b00);
> >	   b = !(x == 2'b00) && !(y == 2'b00);
> >	end
> 
> Essentially yes, though it can be expressed more concisely with
> a
> reduction-OR operator:
> 
> 	always_comb begin
> 	   a = (|x) || (|y);
> 	   b = (|x) && (|y);
> 
> Like C, the truth value of a multi-bit vector is based on
> whether it
> is zero.  That truth value is used when a vector is used with a
> logical AND or OR, or as a condition in an if-statement or
> conditional
> operator.
> 
> Steven Sharp
> sharp@cadence.com