[sv-bc] RE: [SystemVerilog Errata 0001275]: 12.3.3: Implicit nets are not necessarily unsigned

In the correction, the reference to 3.5 should be 4.5.

Shalom


> -----Original Message-----
> From: sv@eda.org [mailto:sv@eda.org]
> Sent: Monday, January 30, 2006 10:06 AM
> Subject: [SystemVerilog Errata 0001275]: 12.3.3: Implicit nets
> are not necessarily unsigned
> 
> 
> The following bug has been RESOLVED.
> ===============================================================
> =======
> http://www.eda.org/svdb/bug_view_page.php?bug_id=0001275
> ===============================================================
> =======
> Reported By:                shalom
> Assigned To:
> ===============================================================
> =======
> Project:                    SystemVerilog Errata
> Bug ID:                     1275
> Category:                   V-1364
> Reproducibility:            always
> Severity:                   feature
> Priority:                   normal
> Status:                     resolved
> Type:                       Errata
> Resolution:                 open
> ===============================================================
> =======
> Date Submitted:             01-05-2006 07:00 PST
> Last Modified:              01-30-2006 00:06 PST
> ===============================================================
> =======
> Summary:                    12.3.3: Implicit nets are not
> necessarily unsigned
> Description:
> According to 12.3.3, "Implicit nets shall be considered
> unsigned.", but the
> comments in the example below it (and common sense) contradict
> that.
> 
> input signed [7:0] d; // no explicit net declaration -- net is
> signed
> 
> And I don't know what this sentence means --
> 
> "Nets connected to ports without and explicit net declaration
> shall be
> considered unsigned, unless the port is declared as signed."
> 
> Why would it affect the signedness of nets to be connected to a
> port?
> 
> -- Brad
> 
> 
> 
> Fix:
> In 12.3.3, REPLACE
> 
> Implicit nets shall be considered unsigned. Nets connected to
> ports
> without an explicit net declaration shall
> be considered unsigned, unless the port is declared as signed.
> 
> WITH
> 
> Nets connected to ports without an explicit net declaration
> shall be
> considered unsigned, unless the port is declared as signed.
> Other implicit
> nets (see 3.5) shall be considered unsigned.
> 
> 
> and REPLACE
> 
> input [7:0] a; // no explicit declaration - net is unsigned
> 
> WITH
> 
> input [7:0] a; // no explicit net declaration - net is unsigned
> 
> 
> and REPLACE
> 
> output [7:0] e; // no explicit declaration - net is unsigned
> 
> WITH
> 
> output [7:0] e; // no explicit net declaration - net is
> unsigned
> ===============================================================
> =======
> 
> ---------------------------------------------------------------
> -------
>  mmaidment - 01-30-2006 00:06 PST
> ---------------------------------------------------------------
> -------
> On January 9, 2006 the SV-BC unanimously approved the proposal
> in the
> description.
> 
> Bug History
> Date Modified  Username       Field                    Change
> ===============================================================
> =======
> 01-05-06 07:00 shalom         New Bug
> 01-05-06 07:00 shalom         Type                      =>
> Errata
> 01-30-06 00:06 mmaidment      Bugnote Added: 0002345
> 01-30-06 00:06 mmaidment      Status                   new =>
> resolved
> ===============================================================
> =======