Re: [sv-bc] Opinion on merging of P1364 and P1800

Non-member submission from Faisal Haque

 

________________________________

From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Faisal Haque (fhaque)
Sent: Tuesday, January 31, 2006 10:54 AM
To: Bresticker, Shalom; Karen Pieper; sv-bc@eda.org; sv-ac@eda.org;
sv-ec@eda.org; sv-cc@eda.org
Subject: [sv-ec] RE: [sv-ac] Opinion on merging of P1364 and P1800

 

Shalom,

Thanks for the response.

 I think we need to merge not only the two LRMs but the two committees
and send a clear message about the SystemVerilog and Verilog being one
language.

The tough question for me is when should it be done and how long will it
take. 

I definitely think it should be done before we start doing any feature
additions to SystemVerilog. However we do have errata to fix.

I am not sure whether it will be more efficient to fix errata on the
combined LRM or on separate LRMs.

 

If it is possible to merge the two LRMs and fix the errata at the same
time then I would be in favor of doing the LRM merge now, otherwise it
should be done after the errata have been fixed. 

 

-Faisal

	 

	
________________________________


	From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
	Sent: Monday, January 30, 2006 10:51 PM
	To: Faisal Haque (fhaque); Karen Pieper; sv-bc@eda.org;
sv-ac@eda.org; sv-ec@eda.org; sv-cc@eda.org
	Subject: RE: [sv-ac] Opinion on merging of P1364 and P1800

	Hi, Faisal.

	 

	Without stating my own position (yet) on whether it should be
done, I think these are the main claims:

	 

	-         Going forward, Verilog should cease to exist as a
separate entity from SystemVerilog, since it is a subset of
SystemVerilog.

	-         The Verilog LRM contains statements, e.g.,
restrictions, which are no longer true in SystemVerilog.

	-         It is difficult and wasteful to maintain 2 LRMs.

	-         SystemVerilog needs a single document which fully
describes it. Today you have 2 LRMs, whose combination describes SV. But
then you have to throw away from the Verilog LRM the statements which
are no longer true in SV.

	-         Some people have the wrong impression that Verilog and
SV are 2 entirely separate incompatible languages instead of SV being a
superset of Verilog.

	 

	Regards,

	Shalom

	 

	
________________________________


	From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf
Of Faisal Haque (fhaque)
	Sent: Monday, January 30, 2006 11:46 PM
	To: Karen Pieper; sv-bc@eda.org; sv-ac@eda.org; sv-ec@eda.org;
sv-cc@eda.org
	Subject: RE: [sv-ac] Opinion on merging of P1364 and P1800

	 

	Karen,

	What is the rationale for merging the two LRMs?

	Can someone explain.

	-Faisal

	 

		 

		
________________________________


		From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org]
On Behalf Of Karen Pieper
		Sent: Friday, January 27, 2006 5:41 PM
		To: sv-bc@eda.org; sv-ac@eda.org; sv-ec@eda.org;
sv-cc@eda.org
		Subject: [sv-ac] Opinion on merging of P1364 and P1800

		Hi, all, 

		In the P1800 meeting last week, the Working Group asked
for each of the SV-* committees to provide an opinion on whether or not
to merge the P1364 and the P1800 LRMs into one LRM.  They are interested
in your opinions on:

		1)  How much time will it take us to merge the relevant
parts of the LRM 
		2)  When you recommend merging the LRM (now, toward the
end of the current 2 year revision cycle, next LRM, never)... 
		3)  Any other questions or comments that the committees
recommend the study group consider in their decision to develop the next
PAR.

		Committee chairs, I would appreciate it if you would
develop a response reflective of your committee's opinion and forward it
to me after your next committee meeting, preferably no later than the
15th of February.

		Thank you, 

		Karen Pieper