Re: [sv-bc] Attributes taking runtime constants?

>From: "Stacey Secatch" <stacey.secatch@xilinx.com>

>The 3.1a spec does not include this, and at this time, I have no
>access to the IEEE preliminary versions.

Attributes were added in the IEEE Std 1364-2001 Verilog standard,
not in SystemVerilog.


>Has there been any work into allowing attributes to take values
>from a runtime constant such as a generate variable or a parameter
>rather than only fixed constants?

Genvars and parameters are not runtime constants; they are
elaboration-time constants.  I assume that what you meant was
that they are constants that are not set at parse-time, but can
be set differently for different instances at elaboration time.

The standard allows attributes to be set to expressions that include
such elaboration-time constants.  I proposed this specifically to
allow attributes to be set to values that are different for different
instances, or are propagated down through the design hierarchy.  This
avoided the need to add complicated extensions to attributes themselves
to accomplish the same thing, which was being proposed.


>But I may want "foo" to be changable passed on parameters, or
>it's location in a generate block. The following code is a compile
>error:
>
>localparam my_attr_str = "foo";
>(* my_attr = my_attr_str *)

This is legal Verilog according to the standard, though that does
not guarantee that all implementations will support it.  I am aware
of tools that only allow setting attributes to constant literals,
which is a subset of the full feature.


Steven Sharp
sharp@cadence.com