Brad, The only way to do what you want would be to have a secondary trigger declaration (an arrayed net or similar) and then have a generate that created and always block sensitized to a single bit. You could then iterate over the bits and change the values creating the events to cause the blocks to trigger. This is certainly not pretty, but that is Verilog. There are many reasons why static topology is important for simulation as well as the obvious reasons for the synthesizable subset. I'm not willing to go anywhere near opening this area without a great deal of thought; even with significant consideration, the implications of non-static hierarchical resolution is very significant in terms of what one might have to do during simulation. There may be non-topological impacting subsets of behavior that could (and likely should) be supported by the LRM but this would be a pretty significant enhancement that I don't think I'd want to consider in this round of LRM work. Gord. Brad Pierce wrote: > Gord, > > As noted in http://eda.org/svdb/bug_view_page.php?bug_id=897 , I agree > that there ought to be a generate foreach. But how would that help with > the example of sending messages at run time to each interface instance > in an array? > > -- Brad > > -----Original Message----- > From: Gordon Vreugdenhil [mailto:gordonv@model.com] > Sent: Sunday, February 05, 2006 9:11 PM > To: Brad Pierce > Cc: sv-bc@eda.org > Subject: Re: [sv-bc] Iterating over arrayed and generated instances with > 'foreach' > > Brad, hierarchical references into arrayed instances are required > to have constant index values -- they are hierarchical names, > not selects. SV has, unfortunately, deepened the confusion > between "select" and "hierarchical reference". Unless you > want to have a "generate foreach" (which wouldn't be such a > bad idea if properly restricted), there isn't any way to > dynamically iterate over an array of interfaces or other > instances, including generates. > > Gord > > > Brad Pierce wrote: > >>A natural usage for 'foreach' is to iterate over an array of > > instances, > >>for example, to send a message across each interface instance in an >>array of interfaces. I can't see in the LRM anyplace that explicitly >>says that's legal. >> >> >> >>Likewise, even iterating the old-fashioned way (with 'for'), the LRM >>seems silent about the legality of applying the array querying >>functions, such as $left(), to arrayed instances. >> >> >> >>For generated instances, it's even more important to be able to > > iterate > >>with 'foreach', because generated instances are not necessarily > > contiguous > >> >> >> for (genvar I = 0; I < N; I += 2) begin:GEN >> >> ... >> >> >> >>This is similar to iterating over an associative dimension, which can > > be > >>done with 'foreach', but not generally with 'for'. >> >> >> >>-- Brad >> >> >> >> >> > > -- -------------------------------------------------------------------- Gordon Vreugdenhil 503-685-0808 Model Technology (Mentor Graphics) gordonv@model.comReceived on Sun Feb 5 21:58:38 2006
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