[sv-bc] Question on ?: with "any" data type

The SV LRM claims the ?: is defined for "any" data type.  Is
the following supposed to be legal?  If so, what is the value of z?

    module top;
       integer x[1] = '{ 1 };
       integer y[1] = '{ 2 };
       integer z[5];
       reg cond;

       initial z = cond ? x : y;
    endmodule

In 1364, when "cond" has the value 'x, the result is
defined bitwise by Table 5-20.  But bitwise operations aren't
defined for unpacked types (and would be quite bad for class
handles or similar).  I see 3 choices:
     1) ?: should be restricted to integral types
     2) it must be a sim time error if the condition is 'x for
        a non-integral result
     3) the condition must be restricted to a 2-state value if
        the result is a non-integral type.

I think I'd prefer (3) since that allows "natural" expression of
assignments for class handles, etc. while ensuring that we can
check legality at elab time.

Gord.
-- 
--------------------------------------------------------------------
Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com