RE: [sv-bc] The scope of import items

Surya,

I just put in a proposal on Saturday for this. If we take the semantics
from VHDL, then no, you do not chain the imports of symbols.

See: http://www.eda.org/svdb/bug_view_page.php?bug_id=0001323

Dave


> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Surya
> Pratik Saha
> Sent: Tuesday, February 07, 2006 9:37 PM
> To: sv-bc@eda.org
> Subject: [sv-bc] The scope of import items
> 
> For the given e.g.
> 
> package p1;
> typedef struct packed{byte r1 ; logic signed [4:0] r2;} st1;
> endpackage
> 
> package p2;
> import p1::*;
> typedef struct packed{byte r1 ; logic signed [4:0] r2;} st2;
> endpackage
> 
> module test;
> import p1::*;
> import p2::*;
> st1 var1;
> always @*
> begin
>     var1 = 1;
> end
> endmodule
> 
> item st1 is imported to p1 as well as in test. Is st1 is not visible
to
> test through import of p2 in test?
> 
> LRM does not clrearly state whether the imported items can be imported
to
> other
> scope or not if the importing scope is itself imported to somewhere
else.
> 
> For the above e.g. if p2 iteself only imported to test, is st1 not
visible
> to
> test?
> 
> Regards
> Surya.