Re: [sv-bc] white space at the end of macro text

Independent of the whitespace issue, in the following line, arg1 needs
to be followed by a double-tic

 

    (* foo = "AA``arg1BB``arg2" *) \

 

For example, the following SV example would be illegal without the
double-tics 

 

    `define mac(x,y) assign x``v = y``v

 

    module test (in_v, out_v);

    input in_v;

    output out_v;

 

       `mac(out_,in_);

 

    endmodule

 

-- Brad