Re: [sv-bc] white space at the end of macro text

I don't believe there are any situations in Verilog (i.e. IEEE Std 1364)
where it matters whether white space at the end of macro text is included
in the text substitution.  There is no way in Verilog to expand a macro
inside a string literal, or to create part of a lexical token with a
macro.  So you won't find anything about this in the 1364 LRM, because
it doesn't matter there.

Since SystemVerilog (i.e. IEEE Std 1800) has added quote-creation and
token-pasting operations, it needs to specify the white space treatment
for macro expansion more precisely.

Steven Sharp
sharp@cadence.com