Re: [sv-ec] Re: [sv-bc] Can a function contain a fork/join/any/none?

Fork/join is legal in Verilog functions, and such usage was supported by
Verilog-XL.

    http://www.boydtechinc.com/btf/report/full_pr/276.html

See also the very first response to Dave's question.

    http://www.eda.org/sv-bc/hm/3958.html

-- Brad