>From: "Stuart Sutherland" <stuart@sutherland-hdl.com> >Are you sure old generations of Verilog tools permitted fork-join in >functions? Well, Verilog-XL currently allows it, and all its old documentation we can dig up seems to allow it. It seems unlikely that this was deliberately changed to allow it after disallowing it earlier. It also seems unlikely to have happened by accident. I am pretty sure NC-Verilog has always allowed it (though it did not support fork-join in automatic tasks/functions until recently, so maybe that is what you saw). For synthesis tools, fork-join is presumably not supported at all, so it would not be supported in a function. >I think fork-join >in functions is a barn door that was inadvertently opened at some point, and >that no users know about it or are using it. I think it has been open all along, at least in some tools. You are probably right that no (or almost no) users are using it or would even think of using it. >I have a question for EDA companies on these committees. You have lots of >user-code in your regression suites. I'd like to know if any of your user >code has fork-join in a function. I had already started a build to make this an error and see if it failed any regressions. I will get back to you. Steven Sharp sharp@cadence.comReceived on Fri Feb 17 14:22:52 2006
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