RE: [sv-bc] Aggregate / struct - 2 questions

Cliff,

1. Assignment patterns: We have also seen this problem, and not just
with simulators. It appears that some of the tools implement the SV 3.1a
version, and not the 1800 version.

This looks to be one of the most major headaches in the short term for
writing 1800-compliant code.

Since there is already a significant amount of code that was written
according to 3.1a, and migrating it to 1800 is going to be a major task,
maybe some of the vendors will add a switch or a compiler directive
(maybe using `begin_keywords) to allow both old and new code to work.

I do think that the 1800 approach is better. The subject of nested
assignment patterns needs to be explained better, and there is an open
issue with respect to queues.


2. $display: I think that is a great idea, and important. It's true for
arrays as well. $writemem is not sufficient. Mantis 331 is about
enhancing $display for aggregate types. I'll add your idea to there.

Shalom


> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On
> Behalf Of Clifford E. Cummings
> Sent: Sunday, February 26, 2006 10:34 PM
> To: sv-bc@eda.org
> Subject: [sv-bc] Aggregate / struct - 2 questions
> 
> Hi, All -
> 
> Two aggregate / struct questions below.
> 
> Attached in a separate file is the following example:
> 
> typedef struct {
>    bit  [3:0] dst_addr;
>    bit  [3:0] src_addr;
>    bit [31:0] data;
>    bit  [7:0] crc;
> } pkt_s;
> 
> module test;
>    pkt_s pkt1;
> 
>    initial begin
>      init('{4'h9, 4'h6, 32'h1234ABCD, 8'h00});
>      pkt1.crc = gen_crc(pkt1.data);
>      show_pkt;
>      $finish;
>    end
> 
>    function void init (pkt_s d);
>      pkt1 = d;
>    endfunction
> 
>    function [7:0] gen_crc (int d);
>      for (int i=0;i<8;i++) gen_crc[i]=^d[(i*4)+:4];
>    endfunction
> 
>    function void show_pkt;
>      $display("dst=%h src=%h data=%h crc=%h",
>          pkt1.dst_addr, pkt1.src_addr, pkt1.data, pkt1.crc);
>    endfunction
> endmodule
> 
> Two questions about this example:
> 
> (1)     The init function takes a pkt_s structure as an input.
> When I
> make the following assignment, one SystemVerilog simulator
> passes
> while another reports an error due to the apostrophe in from of
> the {
> 
> If I remove the apostrophe, the other SystemVerilog simulator
> works
> while the first simulator fails because of the missing
> apostrophe.
> 
> init('{4'h9, 4'h6, 32'h1234ABCD, 8'h00});
> 
> 
> This may just be an artifact of the simulator versions that I
> am
> using but I want to make sure that everyone agrees that this
> function
> call SHOULD include the apostrophe (??) (and this will be fixed
> in
> upcoming releases).
> 
> (2)     Second question. Look at the following display command.
> 
> $display("dst=%h src=%h data=%h crc=%h",
>      pkt1.dst_addr, pkt1.src_addr, pkt1.data, pkt1.crc);
> 
> Is there some way to unpack the struct (almost like aggregate
> de-assignment) so that the display command could be written
> something like:
> 
> $display("dst=%h src=%h data=%h crc=%h", pkt1);
> 
> and the fields propagate to the separate display formats in the
> field-order declared within the struct? I don't think there is
> such a
> thing, but if there is I would like to hear about it (would be
> nice!)
> 
> Regards - Cliff
> 
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com
> Expert Verilog, SystemVerilog, Synthesis and Verification
> Training