Re: [sv-bc] Union assignment patterns

Stuart Sutherland wrote:
> Speaking from a user's perspective, I would expect that anytime I assigned
> value to a union, or read a value from a union, without specifying a member
> name, the value would apply to the first member in the union declaration.
> This is what I have observed in C programming (I don't know if it is the
> rule, or just the behavior of that C compiler).  It is also how the SUPERLOG

No, it is not C. In C, type of Rhs and Lhs expressions of an assignment should 
be compatible. So if Rhs expression is of union type Lhs also should be union 
type(ditto when union object used as Lvalue).

Probably you are confused with union object's initialization. When declaring
union object, if any initializer is present, is applicable to first member of
union object. Consider this example ...

union sample {
	int first;
	double second;
};

union sample s = {10}; /* braces are needed to make it aggregate type rather
			  than arithmetic type */

is equivalent to

union sample s;
s.first = 10;

> simulator worked, from which SystemVerilog unions were derived.  As I user,
> it is intuitive that when assigning a default value to a union with no
> specific member or type tag, the value would apply to the first union
> member, and the default value would be implicitly cast to the type of the
> first member.
> 
> What is the official semantic rule in C when writing to or reading from a
> union by just referencing the union name?

Read above.

Krishanu

[Greg's proposal. I would like to share my thoughts about packed tagged union
  once I get free time]


-- 
"I want my undefined behavior to make Tanmoy Bhattacharya fly out of my
  nose, so that I can get him to help me fix my code."