Re: [sv-bc] unpacked multi-D array type compatibility

Fair enough.  But array_2 is really a one-dimensional array, too,
because all arrays in Verilog are one-dimensional.  An array in Verilog
is said to be "multidimensional" if its elements are arrays.

The syntax for declaring nested array types without defining them in
typedef stages is just sugar.

-- Brad


-----Original Message-----
From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
Sent: Saturday, March 04, 2006 11:34 PM
To: Brad Pierce; sv-bc@eda.org
Subject: RE: [sv-bc] unpacked multi-D array type compatibility

Aah, but there's the very ambiguity.

You state,
> Type matching of multidimensional arrays is not impacted by
> whether the multiple dimensions are built up in stages with
> typedef.

But does the LRM say that unambiguously?

You say, "Both arrays have 2 unpacked dimensions." That is not at all
clear. That may be the intention, but I don't see that the LRM says that
unambiguously. A reasonable reading of the text would be that array_1 is
a 1-dimensional array of elements whose type is itself a 1-D array. Does
the LRM unambiguously say otherwise?

Shalom

> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On
> Behalf Of Brad Pierce
> Sent: Sunday, March 05, 2006 9:14 AM
> To: sv-bc@eda.org
> Subject: Re: [sv-bc] unpacked multi-D array type compatibility
> 
> They match, because, according to 6.9.1.f, "Two array types
> match if they have the same number of unpacked dimensions and
> their slowest varying dimensions have matching types and the
> same left and right range bounds. The type of the slowest
> varying dimension of a multidimensional array type is itself an
> array type."
> 
> Both arrays have 2 unpacked dimensions.  The slowest-varying
> dimensions have the same left and right bounds (1 and 3).
> Likewise, the types of the slowest-varying dimensions are both
> one-dimensional unpacked arrays of logic from 1 up to 5, so
> they match.
> 
> Type matching of multidimensional arrays is not impacted by
> whether the multiple dimensions are built up in stages with
> typedef.
> 
> -- Brad
> 
> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On
> Behalf Of Bresticker, Shalom
> Sent: Saturday, March 04, 2006 10:22 PM
> To: sv-bc@eda.org
> Subject: [sv-bc] unpacked multi-D array type compatibility
> 
> Hi,
> 
> If I have 2 unpacked arrays:
> 
> Array 1
> =======
> typedef logic typ_a [1:5] ;
> typ_a array_1 [1:3] ;
> 
> Array 2
> =======
> logic array_2 [1:3][1:5] ;
> 
> I hope I got these syntaxes correct.
> 
> What degree of type compatibility (section 6.9) do these two
> arrays have? Where is it stated unambiguously in the LRM?