RE: [sv-bc] unpacked multi-D array type compatibility

> Fair enough.  But array_2 is really a one-dimensional array, too,
> because all arrays in Verilog are one-dimensional.  An array 
> in Verilog
> is said to be "multidimensional" if its elements are arrays.
> 
> The syntax for declaring nested array types without defining them in
> typedef stages is just sugar.

By contrast with VHDL, in which you can create a true n-dimensional
array:

  type twoD_array is array(1 to 3, 5 downto 0) of integer;

distinct from the more common and useful array of 1-d arrays:

  type oneD_array is array(5 downto 0) of integer;
  type array_of_arrays is array(1 to 3) of oneD_array;

array_of_arrays is not compatible with twoD_array.

If Shalom is right that the LRM doesn't yet say so, it would
probably be a good idea for it to contain an explicit statement
of SV's behaviour as described by Brad.

Multi-dmensional arrays have limited practical usefulness in 
VHDL because it is so spectacularly tiresome to slice them,
but the underlying idea provides some interesting possibilities
(like being able to extract arbitrary rectangular "slices").
I assume that, at this late stage, sv-bc would prefer not to
grapple with such delights.  SV has plundered enough existing
languages already; perhaps we should draw the line at
cross-border raids on Matlab and APL :-)
-- 
Jonathan Bromley