RE: [sv-bc] reg vs. logic

One could argue that the 'reg' keyword is being re-used here and is not
the same a 'reg' variable.

 

________________________________

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Bresticker, Shalom
Sent: Monday, March 06, 2006 6:58 AM
To: sv-bc@eda.org
Subject: [sv-bc] reg vs. logic

 

A.5.2 shows the following BNFs:

 

udp_output_declaration ::=

      { attribute_instance } output port_identifier

    | { attribute_instance } output reg port_identifier [ =
constant_expression ]

 

udp_reg_declaration ::= { attribute_instance } reg variable_identifier

 

 

Are these exceptions to the rules that reg and logic are the same, or
oversights in the BNF?

 

Shalom

 

 

Shalom Bresticker

Intel Jerusalem LAD DA

+972 2 589-6852

+972 54 721-1033

I don't represent Intel