Re: [sv-bc] reg vs. logic

At Mac's suggestion, though I fear I'm tilting at windmills:
Given Dave's comment below, may I suggest that SV deprecate
"logic" in favor of "reg"?

In the Verilog-AMS committee, we're struggling to rename the
discipline "logic" to something else since Accellera is planning
to make SystemVerilog-AMS.  "logic" has been a reserved word
in AMS since before there was a SystemVerilog. :)

-Geoffrey


"Rich, Dave" wrote:
> 
> And yes, there remains only one fundamental difference between the 'reg'
> data type and the 'logic' data type: they have different sets of letters
> to spell them.
> 
> Dave


-- 
Geoffrey J. Coram, Ph.D.    Staff CAD Engineer     
Analog Devices, Inc.        Geoffrey.Coram@analog.com 
804 Woburn St., MS-422,     Tel (781) 937-1924
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