RE: [sv-bc] Mantis 1345: 10.4: "illegal" unique if/case issues

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Sun Mar 19 2006 - 04:52:32 PST
Dave Rich recently mentioned how creative engineers and programmers are
in using a programming language.

I would word it a little differently. I would say that language
enhancements enable and cause new usage paradigms that we cannot
foresee. So even if we cannot see a reason for someone to write a unique
case with side-effects in the case items, it is entirely possible that
someone will find a use for it if it is allowed.

Since we do see problems with it, I would prefer to prevent the problem
in advance rather than let the behavior be implementation-dependent and
then have to try to close the Pandora's box after it has already been
opened.

Shalom


> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On
> Behalf Of Brad Pierce
> Sent: Friday, March 17, 2006 3:00 AM
> To: sv-bc@eda.org
> Subject: Re: [sv-bc] Mantis 1345: 10.4: "illegal" unique
> if/case issues
> 
> Stu,
> 
> In the following example does o get i or 3?
> 
> typedef bit [1:0] T ;
> module test ( input T i, output T o ) ;
> always_comb
>    unique case (i)
>      ( o = 0 ) : ;
>      ( o = 1 ) : ;
>      ( o = 2 ) : ;
>      ( o = 3 ) : ;
>    endcase
> endmodule
> 
> For a related Verilog example, see
> 
>    http://www.boyd.com/1364_btf/report/full_pr/566.html
> 
> -- Brad
Received on Sun Mar 19 04:52:48 2006

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