Re: [sv-bc] Referring into generate scope via interface port

Shalom,

 

I retract that.  The example in 20.4.4 shows no such thing.  So I am
working under two assumptions, the second being that -

 

       One can refer across an interface-type port into the generate
scopes of a connected interface instance.

 

-- Brad

 

________________________________

From: Brad Pierce 
Sent: Tuesday, April 04, 2006 7:05 AM
To: sv-bc@eda.org
Subject: Re: [sv-bc] Referring into generate scope via interface port

 

Shalom,

 

No, but my first question is actually answered by the final example in
20.4.4, which makes clear that one can refer across an interface-type
port into the generate scopes of a connected interface.

 

       module bus #(N = 0);

       intf_t #(.num_clients(N)) intf();

 

       for (genvar j=0; j < N; j++) begin: clients

          client_m client (.client_ifc (intf.mps[j].client_mp));

       end

    endmodule

 

My working assumption about my second question is that the BNF for
modport declarations is wrong, because a generated modport can already
provide access to a generated signal, without using a modport
expression, if they are both in the same generate block.

 

   interface intf_t #(num_clients = 0);

     //...

 

     for (genvar i=0; i< num_clients; i++) begin: mps

        bit req;

        modport client_mp (output req);

     end

 

     //...

   endinterface

 

-- Brad

 

________________________________

From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
Sent: Tuesday, April 04, 2006 6:18 AM
To: Brad Pierce; sv-bc@eda.org
Subject: RE: [sv-bc] Referring into generate scope via interface port

 

Brad,

 

Did you ever get an answer to this?

 

Shalom

 

________________________________

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Brad
Pierce
Sent: Tuesday, February 28, 2006 8:42 AM
To: sv-bc@eda.org
Subject: [sv-bc] Referring into generate scope via interface port

 

When an interface is passed through a module port without using a
modport, is it legal to refer into the generate scopes of the interface?

For example, if GEN[5] is a generate scope in the interface and 'sig' is
a wire declared within that scope, can I use an interface port 'ifc' of
a module to get at that wire?

     assign ifc.GEN[5].sig = 1'b0;

Apparently, I cannot list generated signals in a modport without using
the modport expression syntax. According to Syntax 20-1 the following is
not legal

    modport mp(input GEN.sig);

and I am forced to do

    modport mp(input .\GEN[5].sig (GEN[5].sig));

Is the BNF correct, or is it just trying to prevent passing out
hierarchical references or fields of a struct without a modport
expression, while forgetting about the possibility of generated signals?

If the BNF is correct, and I pass a modport instead of a naked
interface, then there's suddenly no way to say

   assign ifc.GEN[5].sig = 1'b0;

and I am forced to use modport expressions

   assign ifc.\GEN[5].sig = 1'b0;

-- Brad