30 and 1220, regarding name spaces, are raised to the same Major severity as 1214, which is also about name spaces. 986, regarding Verilog configurations, is raised to Major. Related issues are http://www.boyd.com/1364_btf/report/full_pr/107.html http://www.boyd.com/1364_btf/report/full_pr/108.html http://www.boyd.com/1364_btf/report/full_pr/350.html http://www.boyd.com/1364_btf/report/full_pr/514.html 1366, regarding variables as module path destinations, is raised to Major. 1007 and 1366 should be marked as duplicates of each other. I raised them to Major, to make sure this recurring issue gets discussed by SV-BC, even if only to lower the severity again. There were three items about gaps in the language, which I didn't mark as major, because they are officially enhancements. But they are definitely places where SV has room for improvement. http://eda.org/svdb/bug_view_page.php?bug_id=96 http://eda.org/svdb/bug_view_page.php?bug_id=75 http://eda.org/svdb/bug_view_page.php?bug_id=42 -- BradReceived on Sun Apr 9 11:06:56 2006
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