Re: [sv-bc] Referencing $unit identifiers from within a package

Arturo Salz wrote:

> Dave,
> 
[...]
> 
> Items defined in the compilation-unit scope cannot be accessed by name 
> from outside the compilation unit.

Right -- the compilation unit encloses declarations and design
units.  The enclosed design units have visibility to the
items in the $unit.  No other separate compilation can
"reach into" that $unit and get at the declarations.


Your statement seems to imply that the following should be illegal:

    typedef int foo;
    module M;
      foo x;
    endmodule

And if that is illegal, what exactly is the point of $unit?


Also, how do the LRM rules in 19.3 make sense here:

    When an identifier is referenced within a scope, SystemVerilog
    follows the Verilog name search rules:
       — First, the nested scope is searched (see 12.6 of IEEE Std 1364)
         (including nested module declarations), including any identifiers
          made available through package import declarations.
       — Next, the compilation-unit scope is searched (including any
         identifiers made available through package import declarations).
       — Finally, the instance hierarchy is searched (see 12.5 of IEEE Std 1364).

Note that the "compilation-unit" scope is **explicitly** named as something
that is searched.  Are these rules incorrect?  Or are they only incorrect
for an originating scope that happens to be a package?

The 19.3 rules seem to be pretty clear that Dave's example is legal.

Now, if someone wants to suggest explict rules regarding the
relationship of $unit to enclosed package definitions, I would be
interested in such a clarification, but I think that treating
$unit and enclosed packages in a magic manner is likely to open
up a number of significant questions.

Gord.


>  
> 
> Since in the example, foo is indirectly being exported via the package, 
> I believe this should be illegal.
> 
>  
> 
>             Arturo
> 
>  
> 
> ------------------------------------------------------------------------
> 
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of 
> Rich, Dave
> Sent: Wednesday, April 12, 2006 10:47 AM
> To: sv-bc@eda.org
> Subject: [sv-bc] Referencing $unit identifiers from within a package
> 
>  
> 
> Is the following legal? Should it be legal?
> 
>  
> 
> file.v
> 
> typedef int foo;
> 
> package p;
> 
>   foo A;;
> 
> endpackage
> 
>  
> 
> I’ll hold my opinion so not to taint the response
> 
>  
> 
> Dave
> 
>  
> 
> David Rich
> Verification Technologist
> Design Verification & Test Division
> Mentor Graphics Corporation
> dave_rich@mentor.com
> Office:   408 487-7206
> Cell:     510 589-2625
> 
>  
> 

-- 
--------------------------------------------------------------------
Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com