RE: [sv-bc] $readmemb and always_latch/always_ff

>If you give Design Compiler (for example) two sequential always blocks
>which write to the same variable, you get two flip-flops whose outputs
>are wired together. So the restriction is not arbitrary at all.

As I said, it helps users avoid writing code that won't synthesize
properly.  But from a Verilog language perspective, this limitation
of a particular synthesis tool is arbitrary.  It is possible to
write a valid model of a flip-flop using two sequential always blocks
that write to the same variable.  There is no theoretical reason why
a synthesis tool could not synthesize that correctly into a flip-flop.
It is an arbitrary limitation that it does not.

This is distinct from a combinational always block, where two that
write to the same variable will not be a valid model of combinational
logic.  This is inherent in the Verilog language semantics, and has
nothing to do with the arbitrary restrictions of certain tools.

Steven Sharp
sharp@cadence.com