Re: [sv-bc] Proposal to make it easier to use packages with port declarations

Following up on  http://www.eda.org/sv-bc/hm/2546.html .

 

Is it correct that a package "import statement affects declarations in
the scope that contains the import, regardless of the relative order of
the declarations and imports statements"?

 

If so, does a package import affect ANSI-style module port declarations?
For example, 

   module ( input [WIDTH-1:0] data, 
            input instruction_t a, 
            output [WIDTH-1:0] result 
          ); 
      import shared_decls::* // this defines WIDTH and instruction_t
used above 
    ... 
  endmodule 

See also

 

    http://www.eda.org/sv-bc/hm/2547.html

    http://www.eda.org/sv-bc/hm/2548.html

 

-- Brad