RE: [sv-bc] Proposal to make it easier to use packages with port declarations

I cannot search the data base at the moment (just on a quick break during
training) but I hope my enhancement request (I consider a bug, not an
enhancement) is still open that addresses this topic.  That request is to
allow import statements in the V2K style parameter port lists.  This allows
keeping an import local to a module, but still making package definitions
visible in port declarations.  I have a strong aversion to using $unit.  It
makes it too easy to have duplicate definitions, spaghetti code, compilation
order dependencies, and differences between multi-file compilation versus
single-file compilation.  I am also averse to explicitly referencing
packages for each port declarations.  That works for two or three ports, but
not when dozens of ports are based on user-defined types defined in a
package.  Importing packages in the parameter port list solves all those
problems.

Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
stuart@sutherland-hdl.com
+1-503-692-0898
  

> -----Original Message-----
> From: owner-sv-bc@server.eda.org 
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Warmke, Doug
> Sent: Tuesday, April 25, 2006 8:36 AM
> To: Brad Pierce; sv-bc@server.eda.org
> Subject: RE: [sv-bc] Proposal to make it easier to use 
> packages with port declarations
> 
> Brad,
>  
> That example is illegal.
>  
> You have to place the
>  
>   import shared_decls::*;
>  
> statement in $unit scope, somewhere
> before the module declaration in the input stream.
>  
> The compiler needs to see any types etc. used in
> port declarations before the ports are declared.
>  
> Regards,
> Doug
> 
> 
> ________________________________
> 
> 	From: owner-sv-bc@server.eda.org 
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Brad Pierce
> 	Sent: Tuesday, April 25, 2006 8:33 AM
> 	To: sv-bc@server.eda.org
> 	Subject: Re: [sv-bc] Proposal to make it easier to use 
> packages with port declarations
> 	
> 	
> 
> 	Following up on  http://www.eda.org/sv-bc/hm/2546.html .
> 
> 	 
> 
> 	Is it correct that a package "import statement affects 
> declarations in the scope that contains the import, 
> regardless of the relative order of the declarations and 
> imports statements"?
> 
> 	 
> 
> 	If so, does a package import affect ANSI-style module 
> port declarations?  For example, 
> 
> 	   module ( input [WIDTH-1:0] data, 
> 	            input instruction_t a, 
> 	            output [WIDTH-1:0] result 
> 	          ); 
> 	      import shared_decls::* // this defines WIDTH and 
> instruction_t used above 
> 	    ... 
> 	  endmodule 
> 
> 	See also
> 
> 	 
> 
> 	    http://www.eda.org/sv-bc/hm/2547.html
> 
> 	    http://www.eda.org/sv-bc/hm/2548.html
> 
> 	 
> 
> 	-- Brad
> 
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