RE: [sv-bc] Proposal to make it easier to use packages with port declarations

Today, either you have the import shared_decls::* before the module
declaration.
Or you use full package references: shared_decls::WIDTH
 
shared_decls::instruction_t
 
Francoise
       '


  _____  

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Brad
Pierce
Sent: Tuesday, April 25, 2006 2:42 PM
To: sv-bc@eda.org
Subject: Re: [sv-bc] Proposal to make it easier to use packages with port
declarations



How about the following?  Also illegal?

 

  module m (data, a, result);

    input [WIDTH-1:0] data; 
    input instruction_t a; 
    output [WIDTH-1:0] result;
    import shared_decls::* // this defines WIDTH and instruction_t used
above 
    ... 
  endmodule

 

-- Brad


  _____  


From: Warmke, Doug [mailto:doug_warmke@mentor.com] 
Sent: Tuesday, April 25, 2006 8:36 AM
To: Brad Pierce; sv-bc@eda.org
Subject: RE: [sv-bc] Proposal to make it easier to use packages with port
declarations

 

Brad,

 

That example is illegal.

 

You have to place the

 

  import shared_decls::*;

 

statement in $unit scope, somewhere

before the module declaration in the input stream.

 

The compiler needs to see any types etc. used in

port declarations before the ports are declared.

 

Regards,

Doug

 


  _____  


From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On
Behalf Of Brad Pierce
Sent: Tuesday, April 25, 2006 8:33 AM
To: sv-bc@server.eda.org
Subject: Re: [sv-bc] Proposal to make it easier to use packages with port
declarations

Following up on  http://www.eda.org/sv-bc/hm/2546.html .

 

Is it correct that a package "import statement affects declarations in the
scope that contains the import, regardless of the relative order of the
declarations and imports statements"?

 

If so, does a package import affect ANSI-style module port declarations?
For example, 

   module ( input [WIDTH-1:0] data, 
            input instruction_t a, 
            output [WIDTH-1:0] result 
          ); 
      import shared_decls::* // this defines WIDTH and instruction_t used
above 
    ... 
  endmodule 

See also

 

    http://www.eda.org/sv-bc/hm/2547.html

    http://www.eda.org/sv-bc/hm/2548.html

 

-- Brad