Re: [sv-bc] Proposal to make it easier to use packages with port declarations

I don't particularly like the imports in the arg
list since that appears to bind them to the list
which I don't think is the intent.

Seems to me that a more obvious syntax is a variant
of what the VHDL approach takes.

Since

    import shared_decls::*;
    extern module M
      ...

already has defined meaning, why not allow:

     extern module import shared_decls::*;
                   import shared_decls2::something;
            M  #(...) (...);

and have the "import" list that occurs between the
keyword and the name apply to only that design unit.

I don't think we end up with any parse issues and,
although ugly, the syntax does give a nice hook.  I think
this may be a bit more obvious than having the import
in either the parameter or port list.

Gord.



Brad Pierce wrote:

> So to make full use of packages I need to also use $unit?  Painful.
> 
>  
> 
> I’d much prefer to be able to list the import in the parameter 
> declarations, and, of course, localparams and typedefs, too.
> 
>  
> 
>   package shared_decls;
>      localparam WIDTH = 32;
>      typedef struct packed { 
>      logic [ 7:0] opcode;
>      logic [23:0] addr;
>      } instruction_t;
>   endpackage : shared_decls
> 
>   extern module M
>     #(
>        import shared_decls::*,
>        typedef logic [WIDTH-1:0] T,
>        parameter SIZE = 2048
>      )(
>        input T data,
>        input instruction_t a,
>        output T result>
>      );
> 
>  
> 
>  
> 
> ------------------------------------------------------------------------
> 
> From: francoise martinolle [mailto:fm@cadence.com]
> Sent: Tuesday, April 25, 2006 1:01 PM
> To: 'Brad Pierce'; sv-bc@eda.org
> Subject: RE: [sv-bc] Proposal to make it easier to use packages with 
> port declarations
> 
>  
> 
> Today, either you have the import shared_decls::* before the module 
> declaration.
> 
> Or you use full package references: shared_decls::WIDTH
> 
>                                                     
> shared_decls::instruction_t
> 
>  
> 
> Francoise
> 
>        '
> 
>      
> 
>     ------------------------------------------------------------------------
> 
>     From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
>     Brad Pierce
>     Sent: Tuesday, April 25, 2006 2:42 PM
>     To: sv-bc@eda.org
>     Subject: Re: [sv-bc] Proposal to make it easier to use packages with
>     port declarations
> 
>     How about the following?  Also illegal?
> 
>      
> 
>       module m (data, a, result);
> 
>         input [WIDTH-1:0] data;
>         input instruction_t a;
>         output [WIDTH-1:0] result;
>         import shared_decls::* // this defines WIDTH and instruction_t
>     used above
>         ...
>       endmodule
> 
>      
> 
>     -- Brad
> 
>     ------------------------------------------------------------------------
> 
>     From: Warmke, Doug [mailto:doug_warmke@mentor.com]
>     Sent: Tuesday, April 25, 2006 8:36 AM
>     To: Brad Pierce; sv-bc@eda.org
>     Subject: RE: [sv-bc] Proposal to make it easier to use packages with
>     port declarations
> 
>      
> 
>     Brad,
> 
>      
> 
>     That example is illegal.
> 
>      
> 
>     You have to place the
> 
>      
> 
>       import shared_decls::*;
> 
>      
> 
>     statement in $unit scope, somewhere
> 
>     before the module declaration in the input stream.
> 
>      
> 
>     The compiler needs to see any types etc. used in
> 
>     port declarations before the ports are declared.
> 
>      
> 
>     Regards,
> 
>     Doug
> 
>          
> 
>         ------------------------------------------------------------------------
> 
>         From: owner-sv-bc@server.eda.org
>         [mailto:owner-sv-bc@server.eda.org] On Behalf Of Brad Pierce
>         Sent: Tuesday, April 25, 2006 8:33 AM
>         To: sv-bc@server.eda.org
>         Subject: Re: [sv-bc] Proposal to make it easier to use packages
>         with port declarations
> 
>         Following up on  http://www.eda.org/sv-bc/hm/2546.html .
> 
>          
> 
>         Is it correct that a package “import statement affects
>         declarations in the scope that contains the import, regardless
>         of the relative order of the declarations and imports statements”?
> 
>          
> 
>         If so, does a package import affect ANSI-style module port
>         declarations?  For example,
> 
>            module ( input [WIDTH-1:0] data,
>                     input instruction_t a,
>                     output [WIDTH-1:0] result
>                   );
>               import shared_decls::* // this defines WIDTH and
>         instruction_t used above
>             ...
>           endmodule
> 
>         See also
> 
>          
> 
>             http://www.eda.org/sv-bc/hm/2547.html
> 
>             http://www.eda.org/sv-bc/hm/2548.html
> 
>          
> 
>         -- Brad
> 
>          
> 
>          
> 
>          
> 
>          
> 
>          
> 
>          
> 

-- 
--------------------------------------------------------------------
Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com