OK, I can't resist this one. This was discussed ad nauseum in Accellera SV 3.1. The basic issue debated was whether there was difference between interfaces and modules. As many of you recall, I held the position that an interface was simply the passing of an entire module on a port list (equivalent to what is now a SystemC channel). Others (mostly Peter Flake), held that they were a new unique object intended to model the behavior of interconnect. If we now allow all the same content as modules in interfaces then we should once and for all get rid of the artificial distinction. Modules and interfaces are aliases and modules should be passable as ports. Hi everybody, Jay =================================== Jay Lawrence Senior Architect Functional Verification Cadence Design Systems, Inc. (978) 262-6294 lawrence@cadence.com =================================== ________________________________ From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Brad Pierce Sent: Thursday, April 27, 2006 3:52 PM To: sv-bc@eda.org Subject: [sv-bc] Instantiating gates, primitives and modules in interfaces In http://eda.org/svdb/bug_view_page.php?bug_id=902 Brad suggests allowing gates, primitives and modules to be instantiated inside interfaces. See also Yulik's comments in http://www.eda.org/sv-bc/hm/3473.html . Opinions? -- BradReceived on Fri Apr 28 04:57:56 2006
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