Re: [sv-bc] Interfaces in packages

This is analagous to the use of component declarations in VHDL. We would need to define exactly what could be included in this "local" declaration and then define all the formal (the interface declaration) to local mappings and local to actual (the instantiation) mappings.

Note that the necessity for component declarations is one of those "verbose" things that most Verilog users hate when they are exposed to VHDL.

If this was added they should be allowed in many declarative contexts including modules. This would serve to document the expected interface to a child component.

Jay

Jay Lawrence
Cadence Design Systems, Inc.
Email: lawrence@cadence.com
1 978 262 6294 

-----Original Message-----
From: owner-sv-bc@eda.org
To: Rich, Dave; Brad Pierce; sv-bc@eda.org
Sent: Sun Apr 30 13:25:59 2006
Subject: RE: [sv-bc] Interfaces in packages

Dave,

 

I believe the basic request is to put the interconnect definition in the package, that is, the package does not include the interface instantiation, only its definition. Such usage would make packages a lot more convenient for IP providers who want to export both the physical interconnect and the functional model of a component. Currently, the functional model can be described in a package (as a set of class declarations for example), but the interconnect (the interface) cannot, thus, prohibiting references to the (virtual) interface within the class methods.

 

            Arturo

 

________________________________

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Rich, Dave
Sent: Saturday, April 29, 2006 10:48 PM
To: Brad Pierce; sv-bc@eda.org
Subject: RE: [sv-bc] Interfaces in packages

 

Interfaces, along with modules and programs have their own global namespace, so what purpose does putting them in a package serve?

 

Packages were intended to contain constructs which exist in a local namespace, and generally need to be declared before used.

 

But probably the most significant restriction about packages is that they go through compilation without needing any elaboration. That is why generate statements are not allowed in a package either 

 

Dave

 

 

________________________________

From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On Behalf Of Brad Pierce
Sent: Friday, April 28, 2006 8:48 AM
To: sv-bc@server.eda.org
Subject: [sv-bc] Interfaces in packages

 

Users are expecting packages to contain interface declarations, and are surprised when told that the LRM disallows that.

 

Conceptually, users seem to lump interface declarations together with typedefs and class declarations, perhaps because an interface-type port declaration can specify the name of an interface in place of the generic ‘interface’ keyword.  (However, unlike with classes, a particular specialization of the interface cannot be specified in a port declaration.)

 

Why does the LRM disallow interface declarations in packages?  If there’s not some serious principle forcing this restriction, user demand indicates that the restriction should be lifted.

 

-- Brad