RE: [sv-bc] Is #4.2step legal?

Hi, All -

I agree with Arturo. We need #1step to find the smallest precision 
step in the entire design; otherwise, we will need to build all 
testbenches with very high precisions to ensure that we can sample at 
the smallest step for testing and assertions. I believe that is the 
way it is defined currently.

I would not mind a de-hancement that limited step values to be integers only.

I think it is up to guys like Stu and I to not even mention the 
legality of #4.2step and whenever asked by a student in a class, to 
threaten to take back the student's course completion certificate if 
we ever find them using a decimal point in a step delay! I already 
tell people that there is no known good reason to use a step value 
other than #1step and that using #2step or greater opens the door to 
potential race conditions.

Regards - Cliff

At 12:00 AM 5/12/2006, Arturo Salz wrote:
>Steve,
>
>Unfortunately, defining "step" as anything other than the global time
>precision would render the step unit largely useless for the purpose for
>which it was conceived: To allow users to specify the smallest delay
>possible such that no events can take place at a time in between T and T
>+ 1step. This is useful for specifying the sampling skew of clocking
>blocks.
>Using a non-integer (in the mathematical sense) delay with the step unit
>is in and of itself a strange thing --- people have also questioned the
>utility of a non-unit step, but that is a separate discussion. Since by
>definition a step is the precision of the simulation, a fraction of a
>step is not representable in that precision. So whether, the fraction is
>rounded or truncated, a warning may be appropriate in this case. Note
>that the delay is lexically specified --- it cannot be the result of a
>computation --- so the user must have written that fraction explicitly.
>
>         Arturo
>
>-----Original Message-----
>From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
>Steven Sharp
>Sent: Thursday, May 11, 2006 11:25 AM
>To: sv-bc@eda.org; stuart@sutherland-hdl.com
>Subject: Re: [sv-bc] Is #4.2step legal?
>
>
> >From: "Stuart Sutherland" <stuart@sutherland-hdl.com>
>
> >The text in 1800 Section 3.5 says that a delay time unit of "step" must
>be
> >preceded by either an integer or fixed point value.  This means the
> >following delay is legal:
> >
> >  initial #4.2step $display("Time is %f", $realtime);
> >
> >However, Section 19.10 defines "step" as "The step time unit is equal
>to the
> >global time precision".  Does this mean that a step of "4.2" is rounded
>off,
> >truncated, or illegal?
>
>In the absence of any text specific to this situation, I would expect it
>to work the same way as any delay specified to greater precision than
>the
>time precision.  The delay gets rounded to the time precision.
>
>This brings up a problem with defining step to mean the global time
>precision.  Delays are always rounded to the local timeprecision.  If
>step uses the global time precision, and that is more precise than the
>local time precision, then #4.2step would get rounded to zero.
>
>For example, suppose the global timescale is 1ps/1ps and the local
>timescale is 1ns/1ns.  Then the expression 4.2step would be equivalent
>to 0.0042, and #0.0042 will round to a zero delay.
>
>To make this work reasonably, step needs to mean the local
>timeprecision,
>not the global one.
>
>Steven Sharp
>sharp@cadence.com

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training