[sv-bc] Re: Ballot Issue 228: SystemVerilog should include 2-value net datatypes

From: Brad Pierce <Brad.Pierce_at_.....>
Date: Wed May 17 2006 - 09:10:57 PDT
As noted in http://eda.org/svdb/bug_view_page.php?bug_id=694 , the P1800
ballot issue 228, regarding the need for 2-state datatypes on nets, was
never fixed.

 

What are the key stumbling blocks that still need to be resolved for
this one?

 

-- Brad
Received on Wed May 17 09:10:54 2006

This archive was generated by hypermail 2.1.8 : Wed May 17 2006 - 09:11:11 PDT