Re: [sv-bc] another signing question

> logic [7:0] a,b;
> logic signed [7:0] c;
> assign c = a * b;
> 
> I understand that a * b is unsigned and that c is signed.
> If the MSB of a*b is 1, does c become a negative number?

Yes.  This is no different than standard verilog (substitute
'wire' for 'logic').

Paul