RE: [sv-bc] Is #4.2step legal?

>From: "Arturo Salz" <Arturo.Salz@synopsys.com>

>Unfortunately, defining "step" as anything other than the global time
>precision would render the step unit largely useless for the purpose for
>which it was conceived: To allow users to specify the smallest delay
>possible such that no events can take place at a time in between T and T
>+ 1step. This is useful for specifying the sampling skew of clocking
>blocks.

For this to work, sampling skews would have to ignore the normal time
precision rules that apply to all other delays in Verilog (e.g. delay
controls, continuous assignment and gate delays).  I don't see anything
in the LRM that says that they do.

If you used #4.2step as a delay control in a module whose time precision
was higher than the global time precision, this would get rounded down
to zero.  For example, if the global time precision is 1fs, and the local
time precision and time unit are 1ps, then #4.2step would be equivalent
to #0.0042, which would be rounded to zero.  You cannot specify a delay
in the module with more precision than the module time precision.  That
is what the time precision means.

Steven Sharp
sharp@cadence.com