Re: [sv-bc] default port values

The following is not an answer, but just some details about what is
currently allowed by the LRM.

 

In Verilog, you can initialize a variable output port just like any
other variable.  For example,

 

     module m #(parameter N=8)(input [N-1:0] i, output integer o =
f(N));

        ...

     endmodule

 

is the same as

 

     module m #(parameter N=8)(input [N-1:0] i, output integer o);

     initial o = f(N);

        ...

     endmodule

 

In Verilog, input ports cannot be variables.  In SystemVerilog they can
be, but they cannot be initialized.

 

See Footnote 25 of IEEE SV LRM --

 

      25) ...  It shall be illegal to initialize a port that is not a
variable output port.

 

-- Brad

 

 

________________________________

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Feldman, Yulik
Sent: Thursday, May 25, 2006 1:42 AM
To: sv-bc@eda.org
Cc: Patkin, Guy; Alsop, Thomas R
Subject: [sv-bc] default port values

 

Hi,

 

Is there a good reason why SV doesn't allow default values for ports,
like it allows default values for function/task arguments? Is this
feature missing because there was no request to add it to the language,
or because there was some legitimate reason not to add it? I remember
some old discussion about it, but I can't find the thread.

 

Thanks,

            Yulik.