Re: [sv-bc] Questions on local variable initialization

Stu,

Your first two questions were somewhat answered in  

       http://www.eda.org/sv-bc/hm/4384.html

which is the last entry so far in the thread beginning at

       http://www.eda.org/sv-bc/hm/4367.html


Regarding your third question --

   1)  Lifetime (i.e., static/automatic) is an attribute of a variable,
not of a data type. 

   2)  The SystemVerilog BNF does not and never has accepted lifetime
qualifiers in the declarations of the formal arguments of subroutines.

   3)  The text unambiguously says that it is legal to override the
default lifetimes of the formal arguments of subroutines.

I will open a Mantis item about the conflict between the BNF and the
text. 


You're right that Syntax 6-1 is missing a [var] in data_declaration.
This is a problem in the editorial implementation of the approved (and
very complex) proposal for Closed item

   http://eda.org/svdb/bug_view_page.php?bug_id=168

and is also reminiscent of Closed item

   http://eda.org/svdb/bug_view_page.php?bug_id=532

I will open a Mantis item about the implementation of Syntax 6-1.


-- Brad


-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Stuart Sutherland
Sent: Saturday, May 27, 2006 9:35 PM
To: sv-bc@eda.org
Subject: [sv-bc] Questions on local variable initialization


Can anyone on the committee confirm whether or not the following three
constructs are legal or illegal?

----------------------------------------------------------------
Question 1: Can static variables declared in a begin...end block have
declaration assignments? 

I am getting an error message from a software tool claiming that static
variables in begin...end blocks cannot have in-line initialization
assignments.  Another tool accepts the syntax.  I cannot figure out from
the
SystemVerilog BNF which tool is correct, and I could not find anything
in
the text of the LRM that says either way.  Can anyone tell me if the
following is allowed?

  always_comb begin: foo
    int i = 1;  // initialized first time only
    //...
  end 

The tool that gives an error says that in a begin...end block, only
automatic variables can have a declaration assignment.

----------------------------------------------------------------
Question 2: Can static variables in tasks/functions have declaration
assignments?

Really the same as question 1, but a slightly different context.  Two
tools
disagree on what is legal.


----------------------------------------------------------------
Question 3: What is the syntax to declare a formal argument of an
automatic
task as a static type?

SV LRM clause 12.2 says:
"Verilog allows tasks to be declared as automatic, so that all formal
arguments and local variables are stored on
the stack. SystemVerilog extends this capability by allowing specific
formal
arguments and local variables to be
declared as automatic within a static task, or by declaring specific
formal
arguments and local variables as
static within an automatic task."

None of the software tools I have access to seem to allow the use of
"static" in the formal argument list of a task.  I don't know if I have
the
syntax wrong, or if the tools just don't support the description in
section
12.2 yet.  Can anyone tell me if the following declaration SHOULD be
correct, and if not, what the correct syntax is?

  task automatic check_results (input  packet_t   sent, received,
                                output static int error_count);
    //...
  endtask

----------------------------------------------------------------
Also, I noticed a minor errata in 1800 clause 6.2 during my research on
this.  The BNF excerpt in 6.2 for "data_declaration" does not match the
actual BNF in A.2.1.3.
----------------------------------------------------------------

Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
stuart@sutherland-hdl.com
+1-503-692-0898