Both assignments are legal. You can think of integer as built-in shortcut for typedef logic signed [31:0] integer; Type matching means you can treat an integer as if were a packed array even though you can't declare it as one. The restriction on packed arrays of the predefined types is entirely lexical for two reasons 1. De-facto implementation of Verilog ignore the range on a declaration like integer [31:0] A; This was a Verilog-XL bug turned into a feature that many people used to denote the size of the integer, but is ignored by most implementations. Changing it to mean a packed dimension would not be backwards compatible with the de-facto standard 2. Declaring a packed dimension on any fixed sized data type would be visually confusing. int [15:0] A; looks too much like declaring a 16-bit integer Dave ________________________________ From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On Behalf Of Subhamoy Pal Sent: Thursday, June 01, 2006 9:56 PM To: sv-bc@server.eda.org Subject: Re: [sv-bc] query regarding array assignment pattern Sharmistha Rakshit wrote: Hi, I have query regarding the following testcase:: module top; integer a1 ,a2 ; initial begin a1= '{0:1'b0,3:1'b1,default:1'b0}; I have a more basic query regarding this LRM testcase. The right hand side expression is an array assignment pattern. For array assignment pattern LRM 8.13.1 says "Each expression item shall be evaluated in the context of an assignment to the type of the corresponding element in the array". From this statement it can be inferred that the left hand side for this perticular case is an array. But LRM 5.2 also says: "Integer types with predefined widths cannot have packed array dimensions declared. These types are byte, shortint, int, longint, and integer. Although an integer type with a predefined width n is not a packed array, it matches (see 6.9.2), and can be selected from as if it were, a packed array type with a single [n-1:0] dimension." My question is that whether this LRM example (of assigning an array literal to a integer type) is really correct one or not? a2 ='{32{1'b1}}; end endmodule Now by LRM , the first assignment is valid. and LRM also states that "A syntax resembling multiple concatenations can be used in array assignment patterns as well" So , shouldn't the second assignment be also valid ? Thanks, Sharmistha -- SubhamoyReceived on Mon, 5 Jun 2006 08:41:37 -0700
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