Re: [sv-bc] How to debug if a verilog/SV simulation hangs ?

From: Steven Sharp <sharp_at_.....>
Date: Mon Jun 12 2006 - 14:03:57 PDT
>From: Nasim Hussain <Nasim.Hussain@sun.com>

>i have run into bit of a problem and i know this might not be the right
>alias for this, but i am asking for some advice.

I would suggest addressing your query to any coworkers who have
experience with debugging this kind of problem, or your simulator
vendor, or perhaps to the Usenet group comp.lang.verilog.

Ultimately, I suspect the most efficient approach will be to learn
how to use the debug interface to your simulator to find out where
your infinite loop is executing.

Steven Sharp
sharp@cadence.com
Received on Mon Jun 12 14:03:27 2006

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