[sv-bc] Extending the classic simple_bus example

Hello,

I am wondering if anyone has contemplated extending the "classic"
SystemVerilog simple_bus example to support multiple bus drivers. I've
tried a number of ways and so far have settled for something that is
not quite ideal. Specifically, the wired-or lines and "bit-selection"
for arbitration are preformed outside the interface.

To illustrate, the "ideal" (and synthesizable!) solution would behave
something like this:

interface bus #(parameter int N=4) ();

   tri [31:0] data;
   tri [31:0] address;
   tri [31:0] command;

   wire [N-1:0] _busy;
   wor busy;
   assign busy = |_busy;

   wire [N-1:0] request, grant;

   modport cpu (inout data, output address, output command, output
_busy[i], output request[i]);
   modport memory (inout data, input address, input command, input
busy, input grant[i]);

   modport arbiter(input request, output grant);

endinterface // bus

This seems like a relevant issue since most new users, such as myself,
would naturally try and take a simple example one step further.

Comments, ideas, suggestions?

Thanks,

--
Edmond Cote
Research Assistant
Queen's University - Computer Architecture Lab