RE: [sv-bc] implicit declarations in port expressions

Thanks, Shalom and Steve. I've opened 1501 on the issue of implicit
declarations. 

-----Original Message-----
From: owner-sv-bc@server.verilog.org
[mailto:owner-sv-bc@server.verilog.org] On Behalf Of Steven Sharp
Sent: Tuesday, June 13, 2006 10:47 PM
To: sharp@cadence.com; sv-bc@server.verilog.org; Bresticker, Shalom
Subject: RE: [sv-bc] implicit declarations in port expressions


>From: "Bresticker, Shalom" <shalom.bresticker@intel.com>

>4.5 does not have to explain that. 4.5 can just talk about 'port
>declarations', which is equally applicable to both forms, both in the
>module header and after the module header.

Agreed.


>By the way, I think that the title of 12.3.4 should be "List of port
>declarations" instead of "List of ports declarations".

Without looking at it, I would say that depends on whether it is
talking about declarations of a list of ports, or a list of
declarations of ports.

Steven Sharp
sharp@cadence.com