RE: [sv-bc] Defparam -- mixed message from IEEE standards

It's a pain in the neck.

If I just want to add a $dumpvars, for example, I add:

module cucu;
 initial $dumpvars;
endmodule

and add it to the compilation.

Why do I have to add yet another wrapper to the top-level of my
testbench?


> Why, by the way, are Verilog users so fond of elaborating
> simulations with multiple top-level modules?  What would be
> so hard about instantiating all those top modules in a
> trivial top-level wrapper?
 
Shalom