FW: [sv-bc] ordered parameter overrides into named sequential blocks

Resend for Steven

-----Original Message-----
From: owner-sv-bc@server.eda-stds.org
[mailto:owner-sv-bc@server.eda-stds.org] On Behalf Of Steven Sharp
Sent: Friday, June 16, 2006 10:57 PM
To: sv-bc@server.verilog.org; Geoffrey.Coram@analog.com
Subject: Re: [sv-bc] ordered parameter overrides into named sequential
blocks

>From: "Geoffrey.Coram" <Geoffrey.Coram@analog.com>
>
>One may declare parameters in a named sequential block in 1364-2005
>
>My question is: can one override the parameters declared in the block
>using an ordered list of overrides, eg,
>  example #(4, 3.14) inst2();

No, nor with named overrides.

>Does this assign the value 3.14 to myscope.p2?

No.

>I don't see this specifically addressed by
>  12.2.2.1 Parameter value assignment by ordered list
>but it seems logical to correlate the overrides with the declaration
>order of parameters, regardless of whether they are declared at
>module scope or in a named block.

Logical or not, that isn't how it works, because that isn't how it 
worked in Verilog-XL.  Overrides at module instantiation can only affect

parameters declared at the module level.  Parameters inside nested
scopes 
can only be overridden using defparams.

You can complain that this is an ugly nonlocal construct reaching down 
through the hierarchy, but then overriding a parameter declared in a 
nested block is inherently an ugly thing reaching down through the 
hierarchy.  If you want the parameter to be accessible to the module 
instantiation, then it should be declared at the module level.
Declaring 
it in a nested block is effectively a request for it to be hidden.  That

is what nested scopes do.

Steven Sharp