RE: [sv-bc] Errata - variable declaration assignments

Dave,

 

See the thread beginning http://www.verilog.org/sv-bc/hm/4367.html .

 

I did not yet file a Mantis issue, which is why you did not find one.

 

The statement I quoted from the book by Sutherland, Davidmann, and
Flake, says, "SystemVerilog extends Verilog to allow variables declared
within tasks, functions, begin...end blocks, fork...join blocks, or the
compilation unit scope to be declared with in-line initial values".
 
Although your proposal ("Any variable") is correct, I think it does not
emphasize the difference between Verilog and SystemVerilog enough.
 
These are really two separate issues: 1. VDAs are allowed not just at
module level. 2. You want to require static keyword.
 
Since the 2nd part of the proposal is reversing a SV-EC decision, SV-EC
should be cc'ed on the proposal.
 
Shalom

 

 

 

 

________________________________

From: owner-sv-bc@server.eda-stds.org
[mailto:owner-sv-bc@server.eda-stds.org] On Behalf Of Rich, Dave
Sent: Thursday, June 15, 2006 10:58 PM
To: sv-bc@server.verilog.org
Subject: [sv-bc] Errata - variable declaration assignments

 

1364-2005 section 6.2.1 says "Variable declaration assignments to an
array are not allowed. Variable declaration assignments are only allowed
at the module level".

 

 

1800-2005 section 6.4 says "A variable can be declared with an
initializer", and makes no mention of removing the 1364 restrictions,
although there are many examples of usage.

 

Also, the SystemVerilog 3.0 spec section 5.5  had the paragraph "Data
declared in a static task, function or block defaults to a static
lifetime and a local scope. If an initializer is used, the keyword
static must be specified to make the code clearer." I think there was
some confusion on when exactly the static keyword would be required.

 

I can't find an existing mantis item, but I will file this proposal to
change 1800 section 6.4

 

"Any variable may be declared with an initializer. "

 

And then in section 6.6 I would add right after the automatic program
example

 

"Any variable declared in task, function, or block where the default
lifetime is static and has a declaration assignment shall have an
explicit lifetime. This makes it clear that the initialization of the
variable may be separate from the activation of the scope."

 

 

Dave

 

 

 

 

David Rich
Verification Technologist
Design Verification & Test Division
Mentor Graphics Corporation
dave_rich@mentor.com
Office:   408 487-7206
Cell:     510 589-2625