[sv-bc] FW: [sv-ec] Query regarding Macro substitution

 

 

________________________________

From: owner-sv-ec@server.eda-stds.org
[mailto:owner-sv-ec@server.eda-stds.org] On Behalf Of Kausik Datta
Sent: Wednesday, June 21, 2006 3:41 PM
To: sv-ec@server.eda-stds.org
Subject: [sv-ec] Query regarding Macro substitution 

 

 

Hi, 

LRM is not clear about how "``" will be interpreted within escaped
identifier. 
I have the  query on how the macros defined in the following testcase
will look like after substitution. 

Thanks 
Kausik 

 

Kausikd: cat mag1.v 

`timescale 10s/100ns 

`define X(f) \m[ake_``sd    

`define Y    \m[ake_``sd    

module M; 

    `X(kd) I1(); 
    `Y     I2(); 

endmodule 

 

Output of VCS is as follows, but I think that is not correct: 

Kausikd: cat output.v 

`timescale 10 s / 100 ns 
module M; 

        \m[ake_sd  I1(); 
        \m[ake_``sd  I2(); 
endmodule 






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