Re: [sv-bc] Are $signed/$unsigned constant expressions?

Surya,

 

Yes, all conversion system functions, including $signed() and
$unsigned(), can be used in constant expressions, as specified in 17.8
of IEEE Std 1364-2005.

 

-- Brad

 

________________________________

From: owner-sv-bc@eda-stds.org [mailto:owner-sv-bc@eda-stds.org] On
Behalf Of Surya Pratik Saha
Sent: Wednesday, July 12, 2006 10:09 PM
To: sv-bc@eda.org; sv-bc@eda-stds.org
Subject: [sv-bc] Are $signed/$unsigned constant expressions?

 

Hi, 
Verilog 2K LRM does not consider a system function as constant. But
Verilog 2005 enhanced it and considered some system functions as
constant expressions provided their arguments are also constants. 

Verilog 2005: (Section 5. Expressions) 
Constant system function calls are calls to certain built-in system
functions where the arguments are constant 
expressions. When used in constant expressions, these function calls
shall be evaluated at elaboration time. 
The system functions which may be used in constant system function calls
are "pure" functions, i.e. those 
whose value depends only on their input arguments and which have no side
effects. Specifically, the system 
functions allowed in constant expressions are the conversion system
functions listed in 17.8 and the 
mathematical system functions listed in 17.11. 

17.8 Conversion functions listed following system functions: 
$rtoi converts real values to integers by truncating the real value (for
example, 123.45 becomes 123) 
$itor converts integers to real values (for example, 123 becomes 123.0) 
$realtobits passes bit patterns across module ports; converts from a
real number to the 64-bit 
representation (vector) of that real number 
$bitstoreal is the reverse of $realtobits; converts from the bit pattern
to a real number. 

17.11 Math functions includes only  $clog2 (yet to be implemented in
Cheetah). 

SV 1800 LRM further enhances the list so that $bits and array query
functions also can be considered as constant 
expressions. 

So are $signed/$unsigned constant expressions? 
Is the following case valid? 

   module test(); 
      dut dut(); 
   endmodule // test 

   module dut(i, o1, o2, o3, o4); 
      input [3:0] i; 
      output [7:0] o1, o2, o3, o4; 
      reg [7:0]    o2, o3, o4; 
      parameter    P = 2; 
      localparam LP1 = P + 1; 
      localparam signed [2:0] LP2 = LP1 - 1; 
      localparam signed [7:0] LP3 = $signed(LP2[1:0]); // Is it constant
or not 
      assign o1 = LP2 * i + LP3; 
      always @(i) begin : block 
         localparam LQ1 = LP3 * LP3; 
         o2 = LQ1; 
         begin : block2 
            localparam LQ2 = 3'sd1; 
            o3 = LQ2 + $signed(o2); 
         end 
         o4 = foo(i) + foo(1); 

      end 

      function foo; 
         localparam LR1 = P+P; 
         input [2:0] fi; 
         foo = fi * LR1; 
      endfunction // foo 

   endmodule // dut 

MTI-Vlog is failing. 
Synopsys VCS is passing. 

-- 
Regards
Surya.