I voted yes to all of these. > -----Original Message----- > From: owner-sv-bc@eda-stds.org > [mailto:owner-sv-bc@eda-stds.org] On Behalf Of Maidment, Matthew R > > 1030, 1108, 1154, 1283, 1430, 1475 > > SVDB 1030 _X__Resolve per Bugnote(Yes) ___Do Not Resolve per > Bugnote(No) > http://www.verilog.org/svdb/bug_view_page.php?bug_id=1030 > > SVDB 1108 _X__Resolve per Bugnote(Yes) ___Do Not Resolve per > Bugnote(No) > http://www.verilog.org/svdb/bug_view_page.php?bug_id=1108 > > SVDB 1154 _X__Resolve per Bugnote(Yes) ___Do Not Resolve per > Bugnote(No) > http://www.verilog.org/svdb/bug_view_page.php?bug_id=1154 > > SVDB 1283 _X__Resolve per Bugnote(Yes) ___Do Not Resolve per > Bugnote(No) > http://www.verilog.org/svdb/bug_view_page.php?bug_id=1284 > > SVDB 1430 _X__Yes ___No > http://www.verilog.org/svdb/bug_view_page.php?bug_id=1430 > > SVDB 1475 _X__Yes ___No > http://www.verilog.org/svdb/bug_view_page.php?bug_id=1475 > > > -- > Matt Maidment > mmaidmen@ichips.intel.com > > >Received on Fri Jul 14 12:22:36 2006
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