Date: Tue Jul 18 2006 - 07:34:09 PDT
6.6 says that, "Any data declared outside a module ... are global in scope (can be used anywhere after its declaration) ..." This is confusing because 19.3 says that such a scope ends at the end of the compilation unit, which can be a single file. 19.3 explicitly notes the difference from Verilog with respect to compiler directives. I think the statement in 6.6 should be changed to say that the scope is global only within the compilation unit and to refer to 19.3 for more details. Shalom Shalom Bresticker Intel Jerusalem LAD DA +972 2 589-6852 +972 54 721-1033 I don't represent Intel
