Date: Thu Jul 27 2006 - 09:50:17 PDT
See comments below ________________________________ From: owner-sv-bc@server.eda-stds.org [mailto:owner-sv-bc@server.eda-stds.org] On Behalf Of Bresticker, Shalom Sent: Thursday, July 27, 2006 6:53 AM To: sv-bc@server.eda.org Subject: [sv-bc] Nested module questions Two questions about nested modules: [DR>] Actually, three :-) 1. Can a nested module be explicitly instantiated with the same name as the module name? The question is because on the face of it, the nested module name is being defined in the same name space as the instance name. [DR>] You are correct in that the names are defined in the same space. 19.13.f should have included nested modules; they are excluded from 19.13.a. 2. Can a nested module be instantiated before its definition? [DR>] Yes. Only data types and typedefs have this restriction. 3. 19.6 says at the end that a nested module with no ports that is not explicitly instantiated is implicitly instantiated once. The question is, where does this explicit instantiation have to take place? Suppose I have module m1; module nested1; nested2 n2; endmodule module nested2; endmodule endmodule Is this considered an explicit instantiation of nested2 or not, because it is instantiated in nested1, not in m1? [DR>] It is an explicit instantiation of n2, so no implicit instantiation of n2 takes place. Thanks, Shalom Shalom Bresticker Intel Jerusalem LAD DA +972 2 589-6852 +972 54 721-1033 I don't represent Intel
