RE: [sv-bc] Nested module questions

  

Hi,

While there has been discussion and disagreement on question 2 (the
proof that it is a good question...),

no one has yet answered question 1,

and I don't know whether others agree or disagree on the one answer I
got to question 3.

 

Shalom

 

________________________________

From: owner-sv-bc@server.eda-stds.org
[mailto:owner-sv-bc@server.eda-stds.org] On Behalf Of Bresticker, Shalom
Sent: Thursday, July 27, 2006 9:07 PM
To: Rich, Dave; sv-bc@server.eda.org
Subject: RE: [sv-bc] Nested module questions

 

See below.

________________________________

From: owner-sv-bc@server.eda-stds.org
[mailto:owner-sv-bc@server.eda-stds.org] On Behalf Of Rich, Dave
Sent: Thursday, July 27, 2006 7:50 PM
To: Bresticker, Shalom; sv-bc@server.eda.org
Subject: RE: [sv-bc] Nested module questions

 

See comments below

 

________________________________

From: owner-sv-bc@server.eda-stds.org
[mailto:owner-sv-bc@server.eda-stds.org] On Behalf Of Bresticker, Shalom
Sent: Thursday, July 27, 2006 6:53 AM
To: sv-bc@server.eda.org
Subject: [sv-bc] Nested module questions

 

Two questions about nested modules:

[DR>] Actually, three :-)

[Shalom] Yes, it started as 2, then I thought of another one in the
middle.

1.    Can a nested module be explicitly instantiated with the same name
as the module name? The question is because on the face of it, the
nested module name is being defined in the same name space as the
instance name. 

[DR>] You are correct in that the names are defined in the same space.
19.13.f should have included nested modules; they are excluded from
19.13.a. 

[Shalom] I think they are included in 19.13.e, the module name space,
"introduced by the module ... constructs" and includes the definitions
of "modules ... within the enclosing construct."

That still does not answer the question. On the one hand, a regular
module can also be instantiated with the same name as the module name
even though both names are visible within the module. Also, in the
implicit instantiation case described below, the implicit instance name
is the same as the module name. On the other hand, this is different
than a regular module in that both the module name and the instance name
are *defined* within the same name space.

2.    Can a nested module be instantiated before its definition?

[DR>] Yes. Only data types and typedefs have this restriction.

[Shalom] By data types, do you mean data objects? That actually covers
most of the cases in old Verilog. In old Verilog, instead of the data
object rule (declaration must precede use) being described as the
exception, the task/function rule (declaration need not precede use) is
considered the exception.

In any case, it is not clear what rule applies in this case since the
nested module declaration is within the same enclosing module where it
is being used. Who says it is like tasks/functions and not like data
objects?

3. 19.6 says at the end that a nested module with no ports that is not
explicitly instantiated is implicitly instantiated once. The question
is, where does this explicit instantiation have to take place? Suppose I
have

module m1;

module nested1;

nested2 n2;

endmodule

 

module nested2;

endmodule

endmodule

Is this considered an explicit instantiation of nested2 or not, because
it is instantiated in nested1, not in m1?

[DR>] It is an explicit instantiation of n2, so no implicit
instantiation of n2 takes place.

[Shalom] OK if everyone agrees.

 

Thanks,

Shalom