RE: [sv-bc] [Fwd: Issues with IEEE 1364-2005]

Two comments on this proposal:

First, the wording that one of the expressions "shall not be evaluated" is
too strong.  Not evaluating one of the expressions only works for
simulation.  A conditional operator is a MUX in hardware, and the inputs of
MUX will always be evaluated, whether they are selected or not.  For the
standard to work for simulation, synthesis, formal analysis, etc., the
wording has to be relaxed and say that a tool "may" choose not to evaluate
the expression that was not selected.

Second, the proposal states that if the expression2 and expression3 are
compared, the shorter of those expressions will always be left extended with
zeros.  I would expect that if the expression is signed, it will be sign
extended rather than zero extended.  What I'm not sure of with a conditional
operation, is if all expressions have to be signed before sign extension is
done.

Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
stuart@sutherland-hdl.com
+1-503-692-0898
  

> -----Original Message-----
> From: owner-sv-bc@server.eda-stds.org 
> [mailto:owner-sv-bc@server.eda-stds.org] On Behalf Of Brad Pierce
> Sent: Wednesday, August 02, 2006 9:53 AM
> To: sv-bc@server.eda.org
> Cc: WADAMS@freescale.com; michael.burns@freescale.com
> Subject: Re: [sv-bc] [Fwd: Issues with IEEE 1364-2005]
> 
>  
> 
> -----Non-member submission from [Will Adams 
> <wadams@freescale.com>]-----
> Date: Wed, 02 Aug 2006 11:50:03 -0500
> 
> I have made a number of suggestions for changing section 5.1.13
> `Conditional operator'. In the interests of clarity, below is my
> suggested rewrite of this section.
> 
> will adams
> 
> 
> 5.1.13 Conditional operator
> 
> The conditional operator, a ternary operator, shall be right 
> associative
> and its three operands shall be separated by symbols `?' and 
> `:' in the
> format given in Syntax 5-1.
> 
> [Insert Syntax 5-1 from the current definition.]
> 
> The evaluation of a conditional operator shall begin with a logical
> inequality comparison (see 5.1.8) of expression1 with zero, termed the
> `condition'. If the condition evaluates to false (0), then expression2
> shall not be evaluated, and expression3 shall be evaluated and its
> result used as the result of the conditional expression. If the
> condition evaluates to true (1), then expression3 shall not be
> evaluated, and expression2 shall be evaluated and its result 
> used as the
> result of the conditional expression. If the condition evaluates to an
> ambiguous value (x), then both expression2 and expression3 shall be
> evaluated, and their results shall be combined, bit by bit, 
> using Table
> 5-21 to calculate the final result, unless expression2 or 
> expression3 is
> real, in which case the result shall be 0. If the lengths of 
> expression2
> and expression3 are different, the shorter operand shall be lengthened
> to match the longer and zero-filled from the left (the 
> high-order end).
> 
> [Insert Table 5-21 and the example from the current definition.]
> 
>