RE: [sv-bc] [Fwd: Issues with IEEE 1364-2005]

Greg Jaxon pointed out to me that it would be more natural to define

    A ? B   -->   A ?  B : '0

    A ?: B  -->   A ? '1 :  B
 
I agree, and his better definition still works fine as the condition
expression in an if or ?: because the value of a condition expression is
implicitly or-reduced

   if (A ? B ? C)    --> if ( A ? (B ? C : '0) : '0 )

   if (A ?: B ?: C)  --> if ( A ? '1 : (B ? '1 : C) )

-- Brad

-----Original Message-----
From: owner-sv-bc@eda-stds.org [mailto:owner-sv-bc@eda-stds.org] On
Behalf Of Brad Pierce
Sent: Friday, August 11, 2006 12:32 PM
To: sv-bc@eda.org
Cc: michael.burns@freescale.com; Will Adams
Subject: Re: [sv-bc] [Fwd: Issues with IEEE 1364-2005]

A more natural syntax for linearized short-circuiting would be to add
defaults to the existing ?: syntax.

If it were legal to omit the then-leg or else-leg of an ?:

    A ? B   -->   A ? (|B) : 1'b0

    A ?: B  -->   A ? 1'b1 : (|B)

then, where the C language requires

    if (A && B && C) 

in Verilog one could write 

    if (A ? B ? C)

and where the C langauge requires

    if (A || B || C)

in Verilog one could write

    if (A ?: B ?: C)

because

  if (A ? B ? C)   --> if (A ? |(B ? (|C) : 1'b0) : 1'b0)

  if (A ?: B ?: C) --> if (A ? 1'b1 : |(B ? 1'b1 : (|C)))
 
-- Brad