[sv-bc] Clarification on net/var port determination

Sect. 19.8 is (mostly) clear on what the rules are for determining
net/var port kinds in the absence of an explicit designation.
For inputs though, I am not sure that things are stated correctly.

The statement is:
    For input and inout ports, if the port kind is omitted, then
    the port shall default to a net of net type wire.

Note that this doesn't mention anything about the data_type as
is done for output.

This implies (I think) the following:
    1)  module m (input bit a);
        This would be illegal since we can't have 2-state nets
    2)  module m (input logic a);
        This is legal and "a" would be a net.

For outputs the situation is that:
    1) module m (output bit a);
       means that "a" is a var port of type bit.
    2) module m (output logic a);
       means that "a" is a var port of type logic.

Is that correct?

The implication is that one must have "input var logic a"
for an input var port and must have "output wire logic a"
for an output net port.

Is there any compelling reason to have inputs default to net
types while outputs default to vars?  I understand that outputs
must default to vars for compatibility reasons, but there
doesn't seem to be a symmetric argument for input.  Since,
if we ever do have 2-state nets, "output wire bit a" would
require "wire" wouldn't it be more consistent to have
input default to var in the same manner as output?

Gord
-- 
--------------------------------------------------------------------
Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com